1. Field of the Invention
The present invention relates to an active matrix substrate and a display device. More particularly, it relates to an active matrix substrate provided with a thin film transistor and a storage capacitor element at each pixel for driving the liquid crystal layer, and to an active matrix type liquid crystal display device.
2. Description of the Related Art
Active matrix substrates are widely used in active matrix type display devices such as liquid crystal display devices and electroluminescence (EL) display devices. In the conventional active matrix type liquid crystal display devices using such active matrix substrates, a plurality of scanning signal lines and a plurality of data signal lines intersecting with the scanning signal lines are disposed on each substrate, and a thin film transistor (hereinafter also referred to as “TFT”), among others, is disposed at each point of intersection. An image signal is transmitted to each pixel unit by the switching function of the TFT and so forth. It has also been disclosed that each pixel unit be provided with a storage capacitor element (cf. e.g. Japanese Kokai Publication H06-95157, page 1). Such storage capacitor element prevents the image signal from deteriorating due to the self discharge of the liquid crystal layer or the OFF-state current in the TFT during the OFF period of the TFT. Further, the storage capacitor element is utilized not only for storing an image signal during the OFF period of the TFT but also as a route for applying any of various modulated signals in liquid crystal driving, for instance. A liquid crystal display device equipped with storage capacitor elements can realize low electricity consumption and high picture quality.
An example of the structure of a conventional active matrix substrate is now described referring to the drawings.
FIG. 4 is a schematic plan view illustrating the constitution of one pixel in an active matrix substrate equipped with a storage capacitor element and used in a conventional active matrix type liquid crystal display device.
In FIG. 4, a plurality of pixel electrodes 51 are disposed to form a matrix in an active matrix substrate, and a scanning signal line 52 for feeding a scanning signal and a data signal line 53 for feeding a data signal are disposed surrounding those pixel electrodes 51 and intersecting with each other. At each point of intersection of the scanning signal line 52 and data signal line 53, there is disposed a TFT 54 as a switching element to be connected to the pixel electrode 51. The scanning signal line 52 is connected to the gate electrode of that TFT 54, and the TFT 54 is driven and controlled by the scanning signal inputted into the gate electrode. Further, the data signal line 53 is connected to the source electrode of the TFT 54, and a data signal is inputted into the source electrode of the TFT 54. Furthermore, to the drain electrode, there are connected an interconnection electrode 55, one electrode (storage capacitor upper electrode) 55a of a storage capacitor element via the interconnection electrode 55, and the pixel electrode 51 via a contact hole 56. A storage capacitor (common) wiring pattern 57 functions as the other electrode (storage capacitor lower electrode) of that storage capacitor element.
FIG. 5 is a schematic sectional view illustrating a section of the active matrix substrate shown in FIG. 4 as cut along the line A-A′.
In FIG. 5, there is seen a gate electrode 62 disposed on a transparent insulating substrate (insulator substrate) 61 made of glass, plastic or like material and connected to a scanning signal line 52. The scanning signal line 52 and gate electrode 62 are formed of a film or layer of a metal such as titanium, chromium, aluminum or molybdenum or an alloy thereof, or a laminate thereof. The storage capacitor (common) wiring pattern 57, which constitutes the other electrode of the storage capacitor element (storage capacitor lower electrode), is made of the same material as the scanning signal line 52 and gate electrode 62. A gate insulator (gate insulating layer) 63 is disposed to cover the same. The gate insulator 63 is made of an insulation layer such as a silicon nitride or silicon oxide layer. Thereon are disposed, in a manner overlapping with the gate electrode 62, a high-resistivity semiconductor layer 64 made of amorphous silicon, polysilicon or the like, and a low-resistivity semiconductor layer consisting of n+amorphous silicon or the like doped with such an impurity as phosphorus and coming to a source electrode 66a and a drain electrode 66b. Further, a data signal line 53 is disposed so as to connect to the source electrode 66a. Furthermore, an interconnection electrode 55 is disposed so as to connect to the drain electrode 66b, and the interconnection electrode 55 is extended to constitute a storage capacitor upper electrode 55a, which is one of the electrodes of the storage capacitor element, and is connected to a pixel electrode 51 via a contact hole 56. The data signal line 53, interconnection electrode 55 and storage capacitor upper electrode 55a are made of the same material, and a layer of a metal such as titanium, chromium, aluminum or molybdenum or an alloy thereof, or a laminate thereof is used as the material. The pixel electrode 51 is formed, for example, of a transparent conductive layer such as an ITO (indium tin oxide), IZO (indium zinc oxide), zinc oxide or tin oxide layer. The contact hole 56 is formed so as to pass through an interlayer insulating film or layer 68 formed to cover the top of each of the TFT 54, scanning signal line 52, data signal line 53 and interconnection electrode 55. The material of the interlayer insulating layer 68 is, for example, an acrylic resin, silicon nitride, or silicon oxide. An active matrix substrate having such a structure as shown in FIGS. 4 and 5 is disclosed, for example, in Japanese Kokai Publication H09-152625, pages 8-11 and 19, drawings 3 and 4.
In an active matrix substrate having such a structure, the storage capacitor (common) wiring pattern (storage capacitor lower electrode) and scanning signal line are formed in one and the same step, and the storage capacitor upper electrode, data signal line and interconnection electrode are formed in one and the same step for the purposes of simplifying the manufacturing step and reducing the production cost. Further, when the pixel electrode is formed on an interlayer insulating layer, as shown in FIG. 5, the pixel electrode can be overlapped with each signal line, so that the aperture ratio can be increased and, further, the effect of shielding the pixel electrode against the electric field of each signal line can also be produced. On that occasion, the connection between the pixel electrode and drain electrode is secured via the interconnection electrode by forming a contact hole in the interlayer insulating layer on the storage capacitor (common) wiring pattern or scanning signal line pattern to thereby connect the pixel electrode to the storage capacitor upper electrode. The position of the contact hole is not restricted to a site on the storage capacitor upper electrode but may be on the interconnection electrode. However, as shown in FIG. 4, the contact hole is preferably formed at the site of the storage capacitor upper electrode on a pattern of the storage capacitor (common) wiring pattern, since the aperture ratio is not further reduced thereby.
In the storage capacitor element in the active matrix substrate as shown in FIGS. 4 and 5, the presence of a conductive foreign material or a pinhole in the insulating layer between the storage capacitor wiring pattern (storage capacitor lower electrode) and storage capacitor upper electrode may result in a short circuit between the storage capacitor wiring pattern (storage capacitor lower electrode) and the storage capacitor upper electrode, which, in turn, result in a dot defect at the site of the short-circuited pixel in the image displayed; in this respect, there is room for improvement. Further, in the case of short-circuiting between the data signal line and storage capacitor upper electrode, which are formed in one and the same step, due to such a defect as a residual layer, a dot defect may appear in the same manner and the defect cannot be repaired; in this respect, there is also room for improvement.
As the countermeasure for such a dot defect, the method comprising dividing the storage capacitor wiring pattern in the pixel and the method comprising disposing a redundant line in the storage capacitor wiring pattern are disclosed (cf. e.g. Japanese Kokai Publication H01-303415, pages 2-4, drawing 1 and Japanese Kokai Publication H09-222615, pages 3, 4, 6 and 7, drawings 1-3).
In the active matrix substrate in which the storage capacitor wiring pattern is made redundant according to the method of dividing the storage capacitor wiring pattern in the pixel as disclosed in Japanese Kokai Publication H01-303415, the storage capacitor (common) wiring pattern is partly multiplied within each pixel and, further, there is provided a structure such that when a conductive foreign material or a pinhole occurs in the insulating layer between the storage capacitor wiring pattern (storage capacitor lower electrode) and storage capacitor upper electrode and causes short-circuiting, the short-circuited storage capacitor wiring pattern (storage capacitor lower electrode) can be destructed and eliminated by means of a laser, for instance.
However, these methods can indeed destruct and eliminate a short-circuited storage capacitor wiring pattern (storage capacitor lower electrode) by means of a laser, for instance, upon occurrence of a short circuit between the storage capacitor wiring pattern and storage capacitor upper electrode due to the presence of a conductive foreign material or a pinhole in the insulating layer between the storage capacitor wiring pattern (storage capacitor lower electrode) and storage capacitor upper electrode but it is difficult to attain such destruction and elimination without damaging the insulating layer; in this respect, there is room for improvement. Further, when the storage capacitor upper electrode formed in the same step together with the data signal line is short-circuited with the data signal line due to a residual layer, for instance, the short-circuited storage capacitor upper electrode cannot be repaired while allowing the same as a storage capacitor element without resulting in a dot defect; in this respect, there is room for improvement.
Further, a method comprising constituting the storage capacitor electrode as an at least three-layer structure through the intermediary of insulating layers has been disclosed (cf. e.g. Japanese Kokai Publication H07-270824, pages 6-8, drawings 10 and 11). According to this method, the middle layer electrode (storage capacitor lower electrode) of the storage capacitor electrode formed in the form of at least three layers is divided into a plurality of sections and each section is connected to the lower layer electrode (storage capacitor lower electrode) via a contact hole. This gives a structure such that a middle layer electrode (storage capacitor lower electrode) short-circuited with the upper layer electrode (storage capacitor upper electrode) can be destructed and eliminated from the lower layer electrode (storage capacitor lower electrode) by means of a laser or the like and, in the case of a short circuit formed between the storage capacitor element electrodes, the short-circuited storage capacitor electrodes are partly destructed and eliminated by means of a laser or the like; the short circuit of the storage capacitor electrodes can be thus repaired to an extent such that the short circuit of the storage capacitor electrodes will not affect the display quality.
However, this method gives a structure such that each middle layer of a plurality of the divided storage capacitor lower electrodes is connected to the lower storage capacitor electrode in the lower layer via a contact hole and the storage capacitor upper electrode in the upper layer is used as a pixel electrode and, therefore, a simplification of the manufacturing process and a reduction of the manufacturing cost have been demanded.
Furthermore, a liquid display device having a first region comprising an auxiliary capacitor electrode (storage capacitor upper electrode) electrically connected to an interconnection wiring pattern (interconnection electrode) and to a contact hole, a third region formed at a site not overlapping with the auxiliary capacitor common wiring pattern (storage capacitor wiring pattern), and a second region electrically connected to the first region via that third region (cf. e.g. Japanese Kokai Publication 2001-330850, page 1). According to this construction, it is possible, when one of the first and second regions is short-circuited, to function the other region as a storage capacitor element by destructing and eliminating the short-circuited region.
However, the storage capacitor upper electrode formed in the same step as the data signal line is readily short-circuited with the data signal line due to a residual layer or the like, and the method described in Japanese Kokai Publication 2001-330850 cannot repair the first and second regions simultaneously in case of short-circuiting of both of them; in this respect, there is room for contrivance. Furthermore, when the first region of the auxiliary capacitor electrode, which is a part of the storage capacitor element, is short-circuited with the data signal line due to a residual layer, for instance, or when the first region is short-circuited, between layers, with the auxiliary capacitor common wiring pattern (storage capacitor wiring pattern) due to a pinhole or a conductive foreign material, the method described in Japanese Kokai Publication 2001-330850 requires that cleavage be made at the cleavage site X1 in the third region (cf. FIG. 1 in Japanese Kokai Publication 2001-330850) and at the cleavage site X3 of the interconnection wiring pattern (cf. FIG. 1 in Japanese Kokai Publication 2001-330850) and the connection points Y1 and Y2 (cf. FIG. 1 in Japanese Kokai Publication 2001-330850) be electrically connected to connect the interconnection wiring pattern to the second region via an interconnection electrode for repairing; thus, it is necessary to carry out laser irradiation at a total of 4 sites. Therefore, there is still room for contrivance for shortening the time of repairing and the step of repairing.